Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage

This brief presents a new P-parallel radix-2 memory-based fast Fourier transform (FFT) architecture. The aim of this work is to reduce the number multiplexers and achieve an efficient memory usage. One advantage proposed architecture that it only needs permutation circuits after memories, which reduces multiplexer usage one per parallel branch. Another calculates same based on perfect shuffle at each iteration. Thus, shuffling do not need be configured for different iterations. In fact, all memories require read write addresses, simplifies control even further allows merge memories. Along with hardware efficiency, conflict-free access fulfilled by circular counter. FFT has been implemented field programmable gate array. Compared previous approaches, least achieves very low area